Many semiconductor devices are designed to intercommunicate with other semiconductor devices over digital buses. Such devices incorporate drivers to drive digital signals on a bus, and receivers to receive signals driven by other devices on the bus.
As integrated circuit operating voltages decrease—while bus clock speeds increase—it becomes increasingly difficult to drive bus signals in a manner that allows them to be received without errors introduced by noise, reflections, framing errors, etc. Accordingly, impedance matching of bus signaling components is not only desirable, but may be required for some high-speed, low-voltage buses are to work reliably.
Many schemes exist for calibrating driver circuitry, e.g., to achieve a specified drive strength (drive strength is often characterized by an on-resistance “Ron”, which, for a field-effect transistor, is a ratio of source-drain voltage to driver current at a given source-drain voltage). Most calibration schemes work by connecting the driver to a known load, and then adjusting the drive strength until a known voltage is achieved at a designated point in the driver/load path. A self-calibrating circuit typically measures for the known voltage itself. A circuit can also calibrate its drivers by cooperating with a remote circuit that measures a remote voltage and issues driver calibration instructions to the first circuit.
A cooperative calibration scheme has been proposed for DDR-II (Double Data Rate-II) SDRAM (Synchronous Dynamic Random Access Memory) devices. This scheme is known as the Off-Chip Driver (OCD) Impedance Adjustment Protocol, and is described in a document entitled “DDR-II SDRAM: OCD Impedance Adjustment”, dated Nov. 2, 1999. The OCD protocol defines a command that can be issued by a memory controller to a memory device. This command causes the memory device to enter an OCD Impedance Adjustment mode. This mode causes the memory device to reset its driver to a nominal impedance, and then respond to commands from the memory controller to increase or decrease its driver impedance.
FIG. 1 shows one calibration configuration 20 envisioned by the drafters of the OCD Impedance Adjustment Protocol. A memory controller 30 communicates with a DDR-II SDRAM device 50 over a bi-directional data bus (one bus line DQ0 is shown) and a unidirectional address/command bus (44 and 46). Controller 30 and device 50 both connect to circuit board 40, which contains bus traces as well as other connections (power, clocks, etc.) used by the circuits.
Memory controller 30 contains a master driver 32, a comparator 34, a multiplexer 36, and a calibration state machine 38. State machine 38 uses MASTER_CTL to set the impedance of master driver 32. Comparator 34 supplies a calibration match signal CAL_MATCH to state machine 38. CAL_MATCH is used to sense whether the voltage on DQ0 matches a voltage supplied by multiplexer 36. State machine 38 sets multiplexer 36 to pass one of three reference voltages, Voh, Vol, and Vref, to comparator 34, depending on the comparison to be performed.
SDRAM device 50 contains an I/O driver 52 that connects to DQ0. SDRAM control logic 54 receives commands from memory controller 30 over command bus 46. Depending on the command received, some possible operations are a transfer of data from I/O driver 52 to memory array 58 (a write operation), a transfer of data from memory array 58 to I/O driver 52 (a read operation), and a transfer of data from I/O driver 52 to impedance control register 56 (an OCD operation). During a read operation, impedance control register 56 sets the impedance of I/O driver 52 according to the current value held in register 56.
The OCD Impedance Adjustment Protocol explains several methods for calibrating the drivers in system 20. The master driver must be calibrated first. Although master driver calibration is not explained in detail, two methods are prevalent. First, the master driver can be calibrated at the factory, with the appropriate driver settings stored in non-volatile (e.g., fuse-based) registers on the master circuit. Second, a calibration load can be connected from a Vddq/2 voltage reference to a spare master driver for purposes of calibration. The calibration setting for the spare driver is then propagated to the master driver.
With the master driver 32 calibrated, controller 30 uses the OCD Impedance Adjustment Protocol to set the impedance of I/O driver 52. SDRAM 50 is instructed to reset its impedance control register 56 and accept OCD commands. State machine 38 then drives DQ0 low, using the previously calibrated pull-down impedance for driver 32. Controller 32 instructs SDRAM 50 to attempt to drive DQ0 high. While this instruction is active, comparator 34 compares the voltage on DQ0 to Vref (usually set halfway between the supply voltage Vddq and ground). Controller 32 then issues a command to SDRAM 50 to raise or lower the pull-up impedance of driver 52 as appropriate, reissues the read command, and compares the voltages again—this process continues until driver 52's pull-up impedance matches master driver 32's pull-down impedance. This entire process is duplicated to calibrate driver 52's pull-down impedance against master driver 32's pull-up impedance.